Hardware synthesizable algorithm for bovine parasites detection

Abstract

The agricultural and agro-industrial sector is the main generator of incomes in Argentina. In this industry, good parasite control allows to mitigate large economic losses. For this reason, one of the ways to attack the problem is by using medicines on animals. Parasitic analysis is performed by sending samples to specialized veterinary laboratories, which is why treatment is delayed and additional costs are generated for both the producer and the veterinarian.

This is why is valuable to automate the count of parasite eggs in bovines by means of a portable device that can be transferred to the place where these animals live to carry out an in situ diagnosis.

This paper proposes the development of an algorithm that can be synthesized in hardware (IP Core) with FPGA as the target platform for counting parasite eggs using high-level synthesis. The results demonstrate the feasibility of implementation, obtaining 87% accuracy and 77% sensitivity, and operating at a rate of 45 and 62 frames per second for the proposed commercial kits: PYNQ-Z1 and ULTRA96V2, respectively.